Usually, the reading an EEPROM type memory involves a comparison of the current consumed in a cell selected in read mode and a reference cell in the blank state with the two cells being biased under the same voltage conditions. Each cell draws a certain current. Depending on whether the higher current is obtained from one cell or the other, the level of the output of a detector switches to zero or to one. From this, it is determined whether the selected cell is erased or programmed. An EEPROM cell conventionally comprises at least one MOS selection transistor and one MOS floating-gate transistor. It is the MOS floating-gate transistor that is actually written in while the MOS selection transistor is used only to cut off or permit the selection of the memory cell in the matrix of memory cells.
It is known that the principle of the reading of a memory cell of this kind relies on the different threshold voltages that a floating-gate transistor may have, depending on whether it is in the blank, erased or programmed states. In standard EEPROM memory technology, the threshold voltage VthE of an erased cell will be, for example, about 3 volts, the threshold voltage Vthv of a blank cell will be about 0.8 volts and the threshold voltage VthP of a programmed cell will be about -2 volts. The biasing conditions usually chosen are such that the reference cell, which is blank, is on. The gate bias voltage of a floating-gate transistor must therefore be higher than the threshold voltage of a blank cell, namely higher than +0.8 volts. It will be noted that it is therefore necessary to have a read reference voltage generator. The read bias voltage applied to the read/write circuit on the bit line or lines is about 1 volt while the bias voltage applied to the selected word line is in the range of VCC.
At identical read bias voltages, the reference blank cell will consume more current than the erased cell and less current than the programmed cell. The comparison of the currents gives a corresponding binary response. The current drawn by each cell is normally the one dictated by the floating-gate transistor. However, for this purpose, the associated selection transistors must have the capacity to deliver the corresponding current.
Now, at very low voltages, the capacity of the selection transistors to deliver current is reduced. There is therefore a risk of saturation even with very low currents. In this case, it is no longer the floating-gate transistor that dictates the current in the cell but the selection transistor which can no longer give anything more than a borderline saturation current. In other words, if a supply voltage VCC is at a sufficiently high level, for example between 3 and 5 volts, the memory cell (comprising the selection transistor and the floating-gate transistor) may consume between 0 to 40 microamperes under usual read bias conditions. There is therefore a sufficient margin of current to differentiate between the different states of the cell, namely the blank, erased and programmed states. However, when the supply voltage VCC is lowered to 2 volts, the current can no longer vary to the same extent. It is limited by the saturation current of the selection transistor. It is limited, for example, to two microamperes. The margin of differentiation in current becomes extremely small, and even more so as it is necessary to integrate the variations due to the manufacturing method and the dispersion in the cells. The reading of EEPROM type memory cells according to the usual method is therefore no longer reliable at the low or very low voltages.
One approach to this problem of reading at low voltages may include the use of a load pump device for the read operation, in order to recover the usual bias conditions, especially to enable the application of a voltage of 5 volts to the word lines (the gate of the selection transistor). In this way, the selection transistor is capable of meeting the current demand of the memory cell. There would be little adverse effect on the read mode access time, provided that the pump used has a high fan-out and is capable of taking the word line to the desired bias voltage very quickly. Furthermore, this pump would have to work even in standby mode. Otherwise, the time of access to the memory would be heavily penalized.
The drawback of a requirement of this kind is that it considerably increases consumption in standby mode. This additional consumption rules out this approach for portable applications, which make great use of EEPROMs. Furthermore, the fact of using a pump to generate the read bias voltages entails the risk of causing highly inconvenient electrical disturbances. In particular, in the decoder, it is a concern that there may be problems of coupling between signals of the decoder and signals of the oscillator of the pump.
Another approach to the problem could lie in improving the characteristics of the selection transistor so that it is capable of delivering sufficient current at a low voltage. The fan-out of the selection transistor could be increased. However, increasing the fan-out means considerably increasing the size of the transistor. Although this might be acceptable in a simple circuit element, it is heavily disadvantageous for an application to a memory circuit in which there is one selection transistor per memory cell.
It is also possible to further lower the threshold voltage of the selection transistor. However, in practice, this solution is limited by the breakdown voltage which the selection transistor should be capable of withstanding without damage because of the high voltages that are applied to it in erase mode or programming mode. Furthermore, the threshold voltage itself cannot be lower than a borderline voltage dictated by the laws of physics (this borderline voltage may be 200 millivolts for a given technology). Below this borderline voltage, the selection transistor would be conductive in read mode, even if the cell were not selected (hot read operation). The selection transistor would therefore no longer be capable of fulfilling its function of insulating the memory cell in the matrix.